1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and in particular, to a semiconductor device fabrication method that ensures reliable silicidation on a narrow active region.
2. Description of the Related Art
As semiconductor devices develop toward high integration, high performance, and low voltage operation, a low-resistance gate material is required to reduce the gate length of a transistor and a memory cell through the formation of fine patterns and to improve the device's characteristics. The thickness of a gate insulating layer must in turn become smaller to increase a channel current in a transistor and a memory cell for low voltage operation. Furthermore, in order to prevent short channel effects caused by the decrease in the gate length of a transistor and to ensure a margin against punch-through, the junction depth of the source/drain regions should be reduced and the parasitic resistance, that is, the surface resistance and the contact resistance of the source/drain regions should be reduced.
Under these circumstances, studies have been conducted on a self-aligned silicide (salicide) process to reduce the resistivity of a gate and the sheet and contact resistance of source/drain regions. This self-aligned silicide process operates by forming a silicide layer on the surfaces of the gate and the source/drain regions. The salicide process refers to the selective formation of a silicide layer such as a titanium silicide (TiSiX) layer on a gate electrode and source/drain regions.
FIG. 1 is a vertical sectional view of an N-channel MOS (Metal Oxide Semiconductor) transistor fabricated by a conventional salicide process. As shown in FIG. 1, a gate insulating layer 12 is grown by performing a thermal oxidation on the surface of a silicon substrate 10 that has an active region on it, defined by a field oxide film (not shown). A conductive layer such as a polysilicon is then deposited for use as a gate, on the gate insulating layer 12 by CVD (Chemical Vapor Deposition). The polysilicon layer is then doped to be of an N-type by ion implantation and is then patterned into a gate 14 by photolithography.
Subsequently, N.sup.- active regions 16 are formed as lightly doped drain (LDD) regions on the surface of the substrate 10 at opposite sides of the gate 14 by ion-implanting an N-type dopant. In particular, phosphorous (P) may be used at a low dose (e.g., at a dose of 1.times.10.sup.13 -9.times.10.sup.14 ions/cm.sup.2) with the gate 14 being used as an ion-implanting mask.
Spacers 18 are then formed on the sidewalls of the gate 14 by depositing an insulating layer on the resultant structure, including the N.sup.- active regions 16, and then etching back the insulating layer by anisotropical etching such as RIE (Reactive Ion Etching). Here, the insulating layer is formed of a silicidation blocking material, such as a nitride or an oxide. Then, N.sup.+ active regions 20 are formed as high-concentration source/drain regions on the surface of the substrate 10 at opposite sides of the spacers 18 by ion-implanting an N-type dopant. In particular, arsenic (As) may be used at a high dose (e.g., at or above a dose of 1.times.10.sup.15 ions/cm.sup.2) with the spacers 18 and the gate 14 being used as an ion-implanting mask.
Afterwards, a silicide forming metal material, such as titanium (Ti) is deposited on the resultant structure, including the N.sup.+ active regions 20, and the titanium is subjected to rapid thermal annealing (RTA) or thermal treatment using a furnace so that silicidation takes place in an area where the titanium contacts silicon. As a result, a titanium silicide (TiSi.sub.2) layer is formed on the surfaces of the exposed N.sup.- and N.sup.+ active regions 16 and 20 and on the gate 14. Then, an unreacted titanium layer is selectively removed, using an etchant which does not damage the silicide layer 22, the silicon substrate 10, or the gate insulating layer 12.
A problem with the conventional method is incomplete silicidation on the surface of a narrow active region (see "A" of FIG. 1). This is believed to be caused by the impurity concentration in the silicon substrate 10. In other words, with the ion-implantation on the silicon substrate 10 at or above a dose of 1.times.10.sup.15 ions/cm.sup.2, impurities contained in the silicon in excess of their solid solubility limit are segregated or piled up at the titanium/silicon interface, thereby blocking the diffusion of silicon. This phenomenon is observed to be more serious with arsenic than with phosphorous.
As a result, the diffusion of silicon is more difficult in the narrow region A of FIG. 1 between gates 14, than in the remainder of the device. This can lead to incomplete silicidation as compared to a wide region or an increased sheet resistance. For example, when the source region of a transistor, coupled to a common source terminal (V.sub.ss) of memory cells, is narrow, silicon of a substrate is not sufficiently diffused in the narrow region during the step of forming a titanium silicide layer. As a result, the sheet resistance from the source region to a V.sub.ss pattern may increase. In a worse case situation, no silicide layer may be formed at all, thereby reducing a voltage margin in a low-voltage operation area of a device.